CONTENTS
[align=left:33a28d78a1]Foreword xiii
Preface xv
Acknowledgments xviii
Chapter 1Introduction to VHDL1
VHDL Terms2
Describing Hardware in VHDL3
Entity3
Architectures4
Concurrent Signal Assignment5
Event Scheduling6
Statement Concurrency6
Structural Designs7
Sequential Behavior8
Process Statements9
Process Declarative Region9
Process Statement Part9
Process Execution10
Sequential Statements10
Architecture Selection11
Configuration Statements11
Power of Configurations12
Chapter 2Behavioral Modeling15
Introduction to Behavioral Modeling16
Transport Versus Inertial Delay20
Inertial Delay20
Transport Delay21
Inertial Delay Model22
Transport Delay Model23
Simulation Deltas23
Drivers27
Driver Creation27
Bad Multiple Driver Model28
Generics29
Block Statements31
Guarded Blocks35
Chapter 3Sequential Processing39
Process Statement40
Sensitivity List40
Process Example40
Signal Assignment Versus Variable Assignment42
Incorrect Mux Example43
Correct Mux Example45
Sequential Statements46
IF Statements47
CASE Statements48
LOOP Statements50
NEXT Statement53
EXIT Statement54
ASSERT Statement56
Assertion BNF57
WAIT Statements59
WAIT ON Signal62
WAIT UNTIL Expression62
WAIT FOR time_expression62
Multiple WAIT Conditions63
WAIT Time-Out64
Sensitivity List Versus WAIT Statement66
Concurrent Assignment Problem67
Passive Processes70
Chapter 4Data Types73
Object Types74
Signal74
Variables76
Constants77
Data Types78
Scalar Types79
Composite Types86
Incomplete Types98
File Types102
File Type Caveats105
Subtypes105
Chapter 5Subprograms and Packages109
Subprograms110
Function110
Conversion Functions113
Resolution Functions119
Procedures133
Packages135
Package Declaration136
Deferred Constants136
Subprogram Declaration137
Package Body138
Chapter 6Predefined Attributes143
Value Kind Attributes144
Value Type Attributes144
Value Array Attributes147
Value Block Attributes149
Function Kind Attributes151
Function Type Attributes151
Function Array Attributes154
Function Signal Attributes156
Attributes ’EVENT and ’LAST_VALUE157
Attribute ’LAST_EVENT158
Attribute ’ACTIVE and ’LAST_ACTIVE160
Signal Kind Attributes160
Attribute ’DELAYED161
Attribute ’STABLE164
Attribute ’QUIET166
Attribute ’TRANSACTION168
Type Kind Attributes169
Range Kind Attributes170
Chapter 7Configurations173
Default Configurations174
Component Configurations176
Lower-Level Configurations179
Entity-Architecture Pair Configuration180
Port Maps181
Mapping Library Entities183
Generics in Configurations185
Generic Value Specification in Architecture188
Generic Specifications in Configurations190
Board-Socket-Chip Analogy195
Block Configurations199
Architecture Configurations201
Chapter 8Advanced Topics205
Overloading206
Subprogram Overloading206
Overloading Operators210
Aliases215
Qualified Expressions215
User-Defined Attributes218
Generate Statements220
Irregular Generate Statement222
TextIO224
Chapter 9Synthesis231
Register Transfer Level Description232
Constraints237
Timing Constraints238
Clock Constraints238
Attributes239
Load240
Drive240
Arrival Time240
Technology Libraries241
Synthesis243
Translation243
Boolean Optimization244
Flattening245
Factoring246
Mapping to Gates247
Chapter 10VHDL Synthesis251
Simple Gate—Concurrent Assignment252
IF Control Flow Statements253
Case Control Flow Statements256
Simple Sequential Statements257
Asynchronous Reset259
Asynchronous Preset and Clear261
More Complex Sequential Statements262
Four-Bit Shifter264
State Machine Example266
Chapter 11High Level Design Flow273
RTL Simulation275
VHDL Synthesis277
Functional Gate-Level Verification283
Place and Route284
Post Layout Timing Simulation286
Static Timing287
Chapter 12Top-Level System Design289
CPU Design290
Top-Level System Operation290
Instructions291
Sample Instruction Representation292
CPU Top-Level Design293
Block Copy Operation299
Chapter 13CPU: Synthesis Description303
ALU306
Comp309
Control311
Reg321
Regarray322
Shift324
Trireg326
Chapter 14CPU: RTL Simulation329
Testbenches330
Kinds of Testbenches331
Stimulus Only333
Full Testbench337
Simulator Specific340
Hybrid Testbenches342
Fast Testbench345
CPU Simulation349
Chapter 15CPU Design: Synthesis Results357
Chapter 16Place and Route369
Place and Route Process370
Placing and Routing the Device373
Setting up a project373
Chapter 17CPU: VITAL Simulation379
VITAL Library381
VITAL Simulation Process Overview382
VITAL Implementation382
Simple VITAL Model383
VITAL Architecture386
Wire Delay Section386
Flip-Flop Example388
SDF File392
VITAL Simulation394
Back-Annotated Simulation397
Chapter 18At Speed Debugging Techniques399
Instrumentor401
Debugger401
Debug CPUDesign401
Create Project402
Specify Top-Level Parameters403
Specify Project Parameters403
Instrument Signals404
Write Instrumented Design405
Implement New Design405
Start Debug406
Enable Breakpoint406
Trigger Position408
Waveform Display408
Set Watchpoint409
Complex Triggers410
Appendix AStandard Logic Package413
Appendix BVHDL Reference Tables435
Appendix CReading VHDL BNF445
Appendix DVHDL93 Updates449
Alias449
Attribute Changes450
Bit String Literal452
DELAY_LENGTH Subtype452
Direct Instantiation452
Extended Identifiers453
File Operations454
Foreign Interface455
Generate Statement Changes456
Globally Static Assignment456
Groups457
Incremental Binding458
Postponed Process459
Pure and Impure Functions460
Pulse Reject460
Report Statement461
Shared Variables461
Shift Operators463
SLL—shift left logical463
SRL—shift right logical463
SLA—shift left arithmetic463
SRA—shift right arithmetic463
ROL—rotate left464
ROR—rotate right464
Syntax Consistency464
Unaffected466
XNOR Operator466
Index 469
About the Author 477
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